1. Field of the Invention
The present invention relates to a device for electrostatic discharge (hereinafter, referred to as “ESD”) protection and circuit thereof, and more specifically, to a device for ESD protection and circuit thereof in which one ESD device can cope with the whole ESD stress of various modes, which can occur in respective I/O cells (or input cells and output cells), thereby reducing a layout area.
2. Discussion of Related Art
A conventional method of constructing an ESD protection circuit in which an ESD protection device is used in each of I/O cells (or input cell, output cell) is shown in FIGS. 1a and 1b. 
FIG. 1a shows the configuration of a common ESD protection circuit for I/O cells (or input cells and output cells). FIG. 1b shows the configuration of a plurality of I/O cells, input cells and output cells.
An electrode constituting the respective I/O cells (or input cells and output cell) is composed of a power source pad 11, a ground pad 12, and an I/O pad 13. Furthermore, an input pad 14, which is composed of a first PMOS transistor P11 and a first NMOS transistor N11, is connected between the power source pad 11 and the ground pad 12. The gate of each of the first PMOS transistor P11 and the first NMOS transistor N11 is connected to the I/O pad 13. Also, an output pad 15, which is composed of a second PMOS transistor P12 and a second NMOS transistor N12, is connected between the power source pad 11 and the ground pad 12. The drain of each of the second PMOS transistor P12 and the second NMOS transistor N12 is connected to the I/O pad 13. In this configuration, ESD stress current can flow randomly between two electrodes of three electrodes. Therefore, the ESD stress type, which can occur in all electrode combinations of individual I/O cells, can be classified into the following six modes.
(1) Ground pad positive, power source pad floating, I/O pad ground
(2) Ground pad: ground, power source pad: floating, I/O pad positive
(3) Ground pad: floating, power source pad ground, I/O pad positive
(4) Ground pad: floating, power source pad: positive, I/O pad ground
(5) Ground pad: positive, power source pad: ground, I/O pad floating
(6) Ground pad: ground, power source pad: positive, I/O pad floating
In addition, there is pin-to-pin mode ESD stress in which ESD stress is added between the I/O cells and the I/O cell. Accordingly, an ideal ESD protection circuit can protect against all the six ESD stress modes and the pin-to-pin mode ESD stress. The most common ESD protection circuit has the configuration in which three individual ESD protection devices are disposed for each of electrode combinations, as shown in FIG. 1a. 
A first ESD protection device 16 for protecting ESD of the power source pad 11 and the I/O pad 13 is connected between the power source pad 11 and the I/O pad 13. A second ESD protection device 17 for protecting ESD of the ground pad 12 and the I/O pad 13 is connected between the ground pad 12 and the I/O pad 13. A third ESD protection device 18 for protecting ESD of the power source pad 11 and the ground pad 12 is connected between the power source pad 111 and the ground pad 12.
This kind of the mode is advantageous in that it can implement relatively stable ESD protection for the entire I/O cells, but is disadvantageous in that two ESD protection devices have to be separately disposed in one I/O cell. Moreover, there is a problem in that lots of a layout area is taken because an ESD protection device such as a power clamp must be disposed between the power source pad and the ground pad. Furthermore, if the power clamp is not properly disposed between the power source pad and the ground pad, there is a possibility that problems can be generated in a core circuit because ESD stress applied between the two pads is introduced into the core circuit.
Accordingly, the conditions that an ESD protection device and an ESD protection structure, which need to be developed in order to solve the problems of the existing ESD protection structure, are as follows.
(1) It is required that one ESD protection device can protect the six ESD stress modes, which can occur in the respective I/O cells. More particularly, it is required that one ESD protection device cope with ESD protection between the power source pad and the ground pad even without the power clamp.
(2) It is required that the current immunity level of an ESD protection device corresponding to the six ESD stress modes be sufficiently high.
(3) It is required that the output buffer and the input buffer of the I/O cells be efficiently protected against the six ESD stress mode. To this end, a triggering voltage of the ESD protection device has to be similar to a BJT triggering voltage of a PMOS transistor and an NMOS transistor of each output buffer in a corresponding ESD stress mode. It is also required that an ESD stress voltage be lowered lower than the breakdown voltage of a gate oxide film.
(4) Additionally, it is required that a core circuit, an output buffer and an input buffer be protected against the pin-to-pin mode ESD stress in which ESD stress is added between the I/O cells and the I/O cell.